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low voltage, low skew 3.3v lvpecl clock generator 8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 1 g eneral d escription the 8732-01 is a low voltage, low skew, 3.3v lvpecl clock generator. the 8732-01 has two selectable clock inputs. the clk0, nclk0 pair can accept most standard differential input levels. the single ended clock input accepts lvcmos or lvttl input levels. the 8732-01 has a fully integrated pll along with frequency con gurable outputs. an external feedbackinput and outputs regenerate clocks with ?ero delay? the 8732-01 has multiple divide select pins for each bank of outputs along with 3 independent feedback divide select pins allowing the 8732-01 to function both as a frequency multiplier and divider. the pll_sel input can be usedto bypass the pll for test and system debug purposes.in bypass mode, the input clock is routed around the plland into the internal output dividers. features ? ten differential 3.3v lvpecl outputs ? selectable differential clk0, nclk0 or lvcmos/lvttl clk1 inputs ? clk0, nclk0 supports the following input types: lvpecl, lvds, lvhstl, sstl, hcsl ? clk1 accepts the following input levels: lvcmos or lvttl ? maximum output frequency: 350mhz ? vco range: 250mhz to 700mhz ? external feedback for ?ero delay clock regeneration with con gurable frequencies ? cycle-to-cycle jitter: clk0, nclk0, 50ps (maximum) clk1, 80ps (maximum) ? output skew: 150ps (maximum) ? static phase offset: -150ps to 150ps ? lead-free package fully rohs compliant b lock d iagram p in a ssignment 52-lead lqfp 10mm x 10mm x 1.4mm package body y package top view ics8732-01 14 1 5 1 6 17 1 8 1 9 2 0 21 22 2 3 24 2 5 2 6 1 2 5 6 7 1 0 11 1 2 1 3 38 39 35 34 33 31 30 2 9 2 8 27 v cco q a 0 n q a 1 v ee pll _ se l v ee v cco n q a 2 q a 3 n q a 3 v cco n q b 3 q b 2 v ee v ee mr v cco q b1 n q b 0 q b 0 d iv _ sela1 d iv _ selb0 d iv _ sela0 v cc v ee c lk1 nc lk 0 c lk 0 c lk _ sel v cc a nc d iv _ selb1 v cc f bdiv _ sel2 f bdiv _ sel1 f bdiv _ sel0 n fb _ in f b _ in v cc v ee v cco nq fb0 q fb0 nq fb1 q fb1 v ee 4 8 4 9 50 51 52 47 4 6 4 5 44 4 3 42 41 4 0
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 2 t able 1. p in d escriptions number name type description 1, 8, 32, 39, 40 v cco power output supply pins. 2, 3, 4, 5 qa0, nqa0, qa1, nqa1 output differential output pair. lvpecl interface levels. 6, 13, 17, 27, 34, 45, 52 v ee power negative supply pins. 7 pll_sel input pullup selects between the pll and reference clock as the input to the dividers. when low, selects reference clock. when high, selects pll. lvcmos / lvttl interface levels. 9, 10, 11, 12 qa2, nqa2, qa3, nqa3 output differential output pairs. lvpecl interface levels. 14 div_sela1 input pulldown determines output divider valued in table 3. lvcmos / lvttl interface levels. 15 div_sela0 input pulldown determines output divider valued in table 3. lvcmos / lvttl interface levels. 16, 26, 46 v cc power core supply pins. 18 clk1 input pulldown lvcmos / lvttl reference clock input. 19 nclk0 input pullup inverting differential clock input. 20 clk0 input pulldown non-inverting differential clock input. 21 clk_sel input pulldown clock select input. when low, selects clk0, nclk0. when high, selects clk1. lvcmos / lvttl interface levels. 22 v cca power analog supply pin. 23 nc unused no connect. 24 div_selb1 input pulldown determines output divider valued in table 3. lvcmos / lvttl interface levels. 25 div_selb0 input pulldown determines output divider valued in table 3. lvcmos / lvttl interface levels. 28, 29, 30, 31 qb0, nqb0, qb1, nqb1 output differential output pairs. lvpecl interface levels. 33 mr input pulldown active high master reset. when logic high, the internal dividers are reset causing the true outputs qx to go low and the inverted outputs nqx to go high. when low, the internal dividers and the outputs are en- abled. lvcmos / lvttl interface levels. 35, 36, 37, 38 qb2, nqb2, qb3, nqb3 output differential output pairs. lvpecl interface levels. 41, 42, 43, 44 qfb1, nqfb1, qfb0, nqfb0 output differential feedback output pairs. lvpecl interface levels. 47 fb_in input pulldown feedback input to phase detector for regenerating clocks with ?ero delay? 48 nfb_in input pullup feedback input to phase detector for regenerating clocks with ?ero delay? 49 fbdiv_sel0 input pulldown selects divide value for differential feedback output pairs. lvcmos / lvttl interface levels. 50 fbdiv_sel1 input pulldown selects divide value for differential feedback output pairs. lvcmos / lvttl interface levels. 51 fbdiv_sel2 input pulldown selects divide value for differential feedback output pairs. lvcmos / lvttl interface levels. note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values.
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 3 t able 2. p in c haracteristics symbol parameter test conditions minimum typical maximum units c in input capacitance 4 pf r pullup input pullup resistor 51 k r pulldown input pulldown resistor 51 k t able 3a. c ontrol i nput f unction t able for qa0:qa3 o utputs inputs outputs mr pll_sel div_sela1 div_sela0 qa0:qa3, nqa0:nqa3 1 x x x low 0 1 0 0 fvco/2 0 1 0 1 fvco/4 0 1 1 0 fvco/6 0 1 1 1 fvco/8 0 0 0 0 fref_clk/2 0 0 0 1 fref_clk/4 0 0 1 0 fref_clk/6 0 0 1 1 fref_clk/8 t able 3b. c ontrol i nput f unction t able for qb0:qb3 o utputs inputs outputs mr pll_sel div_selb1 div_selb0 qb0:qb3, nqb0:nqb3 1 x x x low 0 1 0 0 fvco/2 0 1 0 1 fvco/4 0 1 1 0 fvco/8 0 1 1 1 fvco/12 0 0 0 0 fref_clk/2 0 0 0 1 fref_clk/4 0 0 1 0 fref_clk/8 0 0 1 1 fref_clk/12
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 4 t able 4a. q x o utput f requency w /fb_in = qfb0 or qfb1 inputs fvco fb_in fbdiv_sel2 fbdiv_sel1 fbdiv_sel0 output divider mode clk1 (mhz) (note 1) minimum maximum qfb 0 0 0 4 62.5 175 (note 2) fref_clk x 4 qfb 0 0 1 6 41.67 116.67 fref_clk x 6 qfb 0 1 0 8 31.25 87.5 fref_clk x 8 qfb 0 1 1 10 25 70 fref_clk x 10 qfb 1 0 0 8 31.25 87.5 fref_clk x 8 qfb 1 0 1 12 20.83 58.33 fref_clk x 12 qfb 1 1 0 16 15.62 43.75 fref_clk x 16 qfb 1 1 1 20 12.5 35 fref_clk x 20 note 1: vco frequency range is 250mhz to 700mhz. note 2: the maximum input frequency that the phase detector can accept is 175mhz. t able 3c. c ontrol i nput f unction t able for qfb0, qfb1 inputs outputs mr pll_sel fbdiv_sel2 fbdiv_sel1 fbdiv_sel0 qfb0, qfb1 nqfb0, nqfb1 1x x x x low 0 1 0 0 0 fvco/4 0 1 0 0 1 fvco/6 0 1 0 1 0 fvco/8 0 1 0 1 1 fvco/10 0 1 1 0 0 fvco/8 0 1 1 0 1 fvco/12 0 1 1 1 0 fvco/16 0 1 1 1 1 fvco/20 0 0 0 0 0 fref_clk/4 0 0 0 0 1 fref_clk/6 0 0 0 1 0 fref_clk/8 0 0 0 1 1 fref_clk/10 0 0 1 0 0 fref_clk/8 0 0 1 0 1 fref_clk/12 0 0 1 1 0 fref_clk/16 0 0 1 1 1 fref_clk/20
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 5 t able 5a. p ower s upply dc c haracteristics , v cc = v cca = v cco = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 3.465 v v cco output supply voltage 3.135 3.3 3.465 v i cc power supply current 165 ma i cca analog supply current 15 ma t able 5b. lvcmos/lvttl dc c haracteristics , v cc = v cca = v cco = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units v ih input high voltage clk1 2 v cc + 0.3 v clk_sel, pll_sel, div_selax, div_selbx, fbdiv_selx, mr 2v cc + 0.3 v v il input low voltage clk1 -0.3 1.3 v clk_sel, pll_sel, div_selax, div_selbx, fbdiv_selx, mr -0.3 0.8 v i ih input high current clk_sel, mr, clk1 div_selax, div_selbx, fbdiv_selx v cc = v in = 3.465v 150 ? pll_sel v cc = v in = 3.465v 5 a i il input low current clk_sel, mr, clk1 div_selax, div_selbx, fbdiv_selx v cc = 3.465v, v in = 0v -5 ? pll_sel v cc = 3.465v, v in = 0v -150 ? a bsolute m aximum r atings supply voltage, v cc 4.6v inputs, v i -0.5v to v cc + 0.5 v outputs, i o continuous current 50ma surge current 100ma package thermal impedance, ja 42.3?/w (0 lfpm) storage temperature, t stg -65? to 150? note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress speci cations only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac charac- teristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 6 t able 5d. lvpecl dc c haracteristics , v cc = v cca = v cco = 3.3v?%, t a = 0? to 70? t able 7. ac c haracteristics , v cc = v cca = v cco = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units f max output frequency 350 mhz t () static phase offset; note 1 pll_sel = 3.3v, fref = 100mhz, fvco = 400mhz -150 150 ps t sk(o) output skew; note 2, 3, 4 150 ps t jit(cc) cycle-to-cycle jitter; note 3 clk0, nclk 50 ps clk1 80 ps t l pll lock time 10 ms t r / t f output rise/fall time 20% to 80% 200 700 ps odc output duty cycle fout 175mhz 48 52 % all parameters measured at f max unless noted otherwise. note 1: de ned as the time difference between the input reference clock and the averaged feedback input signal when the pll is locked and the input reference frequency is stable. note 2: de ned as skew between outputs at the same supply voltage and with equal load conditions. measured at the output differential cross points. note 3: this parameter is de ned in accordance with jedec standard 65. note 4: all outputs in divide by 4 con guration. t able 6. pll i nput r eference c haracteristics , v cc = v cca = v cco = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units f ref input reference frequency 200 mhz t able 5c. d ifferential dc c haracteristics , v cc = v cca = v cco = 3.3v?%, t a = 0? to 70? symbol parameter test conditions minimum typical maximum units i ih input high current clk0, fb_in v cc = v in = 3.465v 150 ? nclk0, nfb_in v cc = v in = 3.465v 5 a i il input low current clk0, fb_in v cc = 3.465v, v in = 0v -5 ? nclk0, nfb_in v cc = 3.465v, v in = 0v -150 ? v pp peak-to-peak input voltage 0.15 1.3 v v cmr common mode input voltage; note 1, 2 v ee + 0.5 v cc - 0.85 v note 1: for single ended applications, the maximum input voltage for fb_in, nfb_in is v cc + 0.3v. note 2: common mode voltage is de ned as v ih . symbol parameter test conditions minimum typical maximum units v oh output high voltage; note 1 v cco - 1.4 v cco - 0.9 v v ol output low voltage; note 1 v cco - 2.0 v cco - 1.7 v v swing peak-to-peak output voltage swing 0.6 1.0 v note 1: outputs terminated with 50 to v cco - 2v.
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 7 p arameter m easurement i nformation c ycle - to -c ycle j itter s tatic p hase o ffset o utput r ise /f all t ime d ifferential i nput l evel o utput s kew 3.3v o utput l oad ac t est c ircuit o utput d uty c ycle /p ulse w idth /p eriod
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 8 a pplication i nformation the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are recommended only as guidelines. fout and nfout are low impedance follower outputs that generate ecl/lvpecl compatible outputs. therefore, termi- nating resistors (dc current path to ground) or current sources must be used for functionality. these outputs are designed to f igure 2b. lvpecl o utput t ermination f igure 2a. lvpecl o utput t ermination drive 50 transmission lines. matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. figures 2a and 2b show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. t ermination for lvpecl o utputs figure 1 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio f igure 1. s ingle e nded s ignal d riving d ifferential i nput w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vcc
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 9 f igure 4c. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 4b. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 4d. clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 4a to 4d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are f igure 4a. clk/ n clk i nput d riven by lvhstl d river 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the 8732-01 provides separate power supplies to isolate any high switching noise from the outputs to the internal pll. v cc, v cca and v cco should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 3 illustrates how a 10 resistor along with a 10 f and a .01 f bypass capacitor should be connected to each v cca pin. f igure 3. p ower s upply f iltering 10 v cca 10 f .01 f 3.3v .01 f v cc p ower s upply f iltering t echniques examples only. please consult with the vendor of the driver component to con rm the driver termination requirements. for example in figure 4a, the input termination applies for lvh- stl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation.
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 10 c16 10uf u1 ics8732-01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 39 38 37 36 35 34 33 32 31 30 29 28 27 52 51 50 49 48 47 46 45 44 43 42 41 40 vcco qa0 nqa0 qa1 nqa1 vee pll_sel vcco qa2 nqa2 qa3 nqa3 vee div_sela1 div_sela0 vcc vee clk1 nclk0 clk0 clk_sel vcca nc div_selb1 div_selb0 vcc vcco nqb3 qb3 nqb2 qb2 vee mr vcco nqb1 qb1 nqb0 qb0 vee vee fbdiv_sel2 fbdiv_sel1 fbdiv_sel0 nfb_in fb_in vcc vee nqfb0 qfb0 nqfb1 qfb1 vcco to logic input pins r13 1k c7 0.1uf rd2 1k r7 50 logic input pin examples r14 1k + - r7 10 div_sela1 vcc vcc fbdiv_sel2 c4 0.1uf vcc=3.3v r9 50 vcc r12 50 + - r1 50 c5 0.1uf vcca r6 50 (u1-1) sp = spare (i.e. not intstalled) (u1-39) zo = 50 div_selb1 r2 50 zo = 50 vcc set logic input to '0' zo = 50 c3 0.1uf bypass capacitors located near the power pins zo = 50 zo = 50 zo = 50 to logic input pins div_sela0 fbdiv_sel1 r11 50 ru2 sp (u1-16) c2 0.1uf r8 50 div_selb0 c8 0.1uf set logic input to '1' fbdiv_sel0 c6 0.1uf rd1 sp (u1-32) c11 0.1uf ru1 1k (u1-26) vcc (u1-40) vcc r10 50 r3 50 (u1-46) lvpecl (u1-8) c1 0.1uf vcc r5 50 r4 50 l ayout g uideline figure 5 shows a schematic example of the 8732-01. in this example, the clk0/nclk0 input is selected. the decoupling capacitors should be physically located near the power pin. for 8732-01, the unused outputs can be left oating. f igure 5. 8732-01 lvpecl b uffer s chematic e xample
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 11 p ower c onsiderations this section provides information on power dissipation and junction temperature for the 8732-01. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the 8732-01 is the sum of the core power plus the power dissipated in the load(s). the following is the power dissipation for v cc = 3.3v + 5% = 3.465v, which gives worst case results. note: please refer to section 3 for details on calculating power dissipated in the load. ? power (core) max = v cc_max * i ee_max = 3.465v * 165ma = 572mw ? power (outputs) max = 30mw/loaded output pair if all outputs are loaded, the total power is 10 * 30mw = 300mw total power _max (3.465v, with all outputs switching) = 572mw + 300mw = 872mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. the maximum recommended junction temperature for the devices is 125?. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming a moderate air ow of 200 linear feet per minute and a multi-layer board, the appropriate value is 36.4?/w per table 8 below. therefore, tj for an ambient temperature of 70? with all outputs switching is: 70? + 0.872w * 36.4?/w = 101.7?. this is well below the limit of 125?. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air ow , and the type of board (single layer or multi-layer). ja by velocity (linear feet per minute) t able 8. t hermal r esistance ja for 52- pin lqfp, f orced c onvection 0 200 500 single-layer pcb, jedec standard test boards 58.0?/w 47.1?/w 42.0?/w multi-layer pcb, jedec standard test boards 42.3?/w 36.4?/w 34.0?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 12 3. calculations and equations. the purpose of this section is to derive the power dissipated into the load. lvpecl output driver circuit and termination are shown in figure 6. t o calculate worst case power dissipation into the load, use the following equations which assume a 50 load, and a termination voltage of v cco - 2v. ? for logic high, v out = v oh_max = v cco_max ? 0.9v (v cco_max - v oh_max ) = 0.9v ? for logic low, v out = v ol_max = v cco_max ? 1.7v (v cco_max - v ol_max ) = 1.7v pd_h is power dissipation when the output drives high. pd_l is the power dissipation when the output drives low. pd_h = [(v oh_max ?(v cco_max - 2v))/r l ] * (v cco_max - v oh_max ) = [(2v - (v cco_max - v oh_max )) /r l ] * (v cco_max - v oh_max ) = [(2v - 0.9v)/50 ] * 0.9v = 19.8mw pd_l = [(v ol_max ?(v cco_max - 2v))/r l ] * (v cco_max - v ol_max ) = [(2v - (v cco_max - v ol_max )) /r l ] * (v cco_max - v ol_max ) = [(2v - 1.7v)/50 ] * 1.7v = 10.2mw total power dissipation per output pair = pd_h + pd_l = 30mw f igure 6. lvpecl d river c ircuit and t ermination
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 13 r eliability i nformation t ransistor c ount the transistor count for 8732-01 is: 4916 t able 9. ja vs . a ir f low t able for 52 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 58.0?/w 47.1?/w 42.0?/w multi-layer pcb, jedec standard test boards 42.3?/w 36.4?/w 34.0?/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 14 p ackage o utline - y s uffix for 52 l ead lqfp t able 10. p ackage d imensions reference document: jedec publication 95, ms-026 jedec variation all dimensions in millimeters symbol bcc minimum nominal maximum n 52 a -- -- 1.60 a1 0.05 -- 0.15 a2 1.35 1.40 1.45 b 0.22 0.32 0.38 c 0.09 -- 0.20 d 12.00 basic d1 10.00 basic e 12.00 basic e1 10.00 basic e 0.65 basic l 0.45 -- 0.75 0 -- 7 ccc -- -- 0.08
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 15 t able 11. o rdering i nformation part/order number marking package shipping packaging temperature 8732ay-01lf ics8732ay-01lf 52 lead ?ead free lqfp tube 0? to +70? 8732ay-01lft ics8732ay-01lf 52 lead ?ead free lqfp tape and reel 0? to +70?
8732-01 data sheet ?2016 integrated device technology, inc revision e january 22, 2016 16 revision history sheet rev table page description of change date b t2 t4a 1 3 4 5 8 features section - changed vco min. from 200mhz to 250mhz. pin characteristics table - changed c in from max. 4pf to typical 4pf. qx output frequency table - changed the clk1 min. column to correlate with the vco change. absolute maximum ratings - changed v o to i o and included continuous current and surge current added differential clock input interface in the application information section. 5/20/03 c t5a 5 power supply dc characteristics table - changed iee from 240ma max. to 165ma max., and icca from 14ma max. to 15ma max. power considerations - recalculated power dissipation and junction tempera- tures to correspond with table 5a. 6/23/03 c 8 10 updated lvpecl output termination diagrams. added schematic layout. 9/24/03 c 1 block diagram - changed ref_sel to clk_sel. 3/3/04 c t11 15 ordering information table - corrected tape & reel count to read 500 from 1000. 4/29/04 c t4a 4 qx output frequency table - changed note 2 from ?00mhz to ?75mhz? 10/19/04 c t11 1 15 features section - added lead free bullet. ordering information table - added lead free part number and note. 5/23/05 c t5a 5 power supply dc characteristics table - corrected i ee to read i cc . 5/31/05 d t5d 6 11 - 12 lvpecl dc characteristics table -corrected v oh max. from v cco - 1.0v to v cco - 0.9v. power considerations - corrected power dissipation to re ect v oh max in table 5d. 4/13/07 e t11 15 17 updated datasheets header/footer with idt from ics. removed ics pre x from part/order number column. added contact page. 7/31/10 e t5d 9 voh maximum = v cco - 0.9 5/2/13 e t11 15 removed ics in the part number where needed. ordering information - removed quantity from tape and reel. deleted lf note below the table. update header and footer. 1/22/16
8732-01 data sheet disclaimer integrated device technology, inc. (idt) reserves the right to modify the products and/or speci cations described herein at any time, without notice, at idt's sole discretion. performance speci cations and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the sam e way when installed in customer products. the information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of i dt's products for any particular purpose, an implied warranty of merchantability, or non-infringe- ment of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expect- ed to signi cantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type de nitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2016 integrated device technology, inc. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales tech support www.idt.com/go/support

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